The invention relates to a bus connecting technique for connecting a processor and functional circuits, which is used in an information processing apparatus, and to components thereof.
As a data rate is enhanced, a time for propagating a wiring between devices becomes increasingly equal to a data cycle. In particular, in a memory technique called a DDR (Double Data Rate)-SDRAM, an operating frequency of a command signal/address signal (hereinafter abbreviated as “C/A signal”) is half of that of a data signal (hereinafter abbreviated as “DQ signal”). For example, in currently available products, data has a transfer rate of 400 Mbps while address has half of the transfer rate of the data, i.e., 200 Mbps.
In an equipment provided with a high-capacity DRAM including a personal computer, server, etc., to mount DRAMs with high density in many cases, 8 to approximately 18 DRAMs are mounted on one module (DIMM: Dual Inline Memory Module) and then 3 or 4 DIMMs are mounted on a motherboard.
FIG. 2 shows one DIMM 2 that is a conventional technique. In the one DIMM 2, DRAMs 10-1 to 10-8 operate in synchronization with one another. In a high-speed memory such as a DDR-SDRAM, a C/A signal 51 is driven to each of the DRAMs 10-1 to 10-8 by a buffer called a register 20. The register 20 once takes the C/A signal 51 from a memory controller 3, and redistributes it to multiple DRAMs 10-1 to 10-8 mounted as a C/A signal 51A on the DIMM 2.
Thus, in the DIMM 2, to a signal line extending to each DRAM from a terminal for signal of the DIMM 2, a DQ signal 52 is connected at an approximately one-to-one rate. In contrast, to the C/A signal 51A extending to each DRAM from the register is connected at an approximately one-to eighteen rate at maximum. The connection form thereof is achieved by a memory access method in which data of each DRAM is read from and written to the same address in the units of DIMM.
References that disclose a wiring technique for clock signals include Patent Document 1 (U.S. Pat. No. 5,243,703) and Patent Document 2 (U.S. Pat. No. 5,319,755). They disclose the technique for using a folded wiring as a clock and generating a intermediate phase of the clocks.
In addition, as a reference disclosing a technique for using a reflected wave of wirings, there is Patent Document 3 (U.S. Patent Application Laid-open No. 2002/018526). This discloses a method of generating a reflected wave at a far end serving as an open end.